Memory modules (e.g., Single In-Line Memory Modules (SIMMs)), Dual In-Line Memory Modules (DIMMs), and Small Outline DIMMs (SODIMMs)) are common in the computer industry, and generally comprise a printed circuit board (PCB) having a number of memory chips thereon. Such memory chips are usually DRAM memory chips, and more typically synchronous DRAMs (e.g., DDRx DRAMs). By incorporating several memory chips on a single PCB, the modules can hold large amounts of data, and thus are useful in computing applications. Generally, data is retrieved from the module by a call from some master device that needs access to the data, e.g., a microprocessor, which typically calls for eight bits of data (i.e., a “byte”) at one time.
A memory module 10 (shown in isolation in FIG. 1A) typically mounts to a system (such as mother board 12) by way of a connector 18, as shown in cross-section in FIG. 1B. In this particular example, the module 10 is a SODIMM module. SODIMM modules are useful in applications such as notebook computers because of their low profiles. This low profile is facilitated by the use of a 90-degree connector 18, which allows the module 10 to be positioned parallel to the mother board 12 when mounted in the connector 18.
The particular memory module 10 illustrated has memory chips 16 on the top (16t) and bottom (16b) of a PCB 14. As one skilled in the art will understand, the PCB 14 further contains contacts 20 at one edge of the PCB 14. These contacts 20 connect to pins on the memory chips 16t and 16b (not shown) via circuit traces in the PCB 14 (not shown). As illustrated, the contacts 20, like the memory chips, appear on the top (20t) and bottom (20b) of the PCB 14. Typically, such contacts are tinned or gold plated to ensure good electrical connection with the connector 18 as discussed further below.
When the memory module 10 is positioned within the connector 18 (e.g., by press fit, by the use of latches, or by other means in the art), as shown in FIG. 1B, the contacts 20 further connect to conductors 22 molded inside of the plastic connector body 18. These conductors 22 are in turn connected to traces on the mother board 12 (not shown) and ultimately to other electrical components on the mother board 12, such as a microprocessor (not shown). Because the conductors 22 communicate with both the top 20t and bottom 20b contacts, the conductors 22 within the connector 18 body will also be split into top (22t) and bottom (22b) conductors.
When the memory module 10 is so coupled to the mother board 12, it will be noticed that the electrical pathway between the contacts 20 and the motherboard 12 differs depending on whether top or bottom contacts are considered. This is because, by necessity, conductors 22t are longer than conductors 22b, e.g., by approximately 10 millimeters. As a result, the signals passing from the chips 16 through the top contacts 20t and top conductors 22t will arrive at the mother board 12 slightly delayed with respect to similar signals passing through the bottom contacts 20b and bottom conductors 22b. 
This difference in length has a small, but potentially critical, effect on the timing of the signals that pass through the conductors 22. For example, suppose a microprocessor on the mother board 12 calls to the memory module to provide a byte of data (from outputs DQ0-DQ7). These signals (e.g., in a DDRx DRAM module) appear on opposite sides of the memory module 10, as shown in FIG. 1C. Specifically, the first four bits, DQ0-DQ3, or “nibble” of data corresponding to pins 5, 7, 15 and 17 on the module, are output on the bottom contacts 20b of the module. The other nibble, DQ4-DQ7, corresponding to pins 4, 6, 16, and 18 of the module 10, are output on the top contacts 20t of the module. (Although a typical DDRx DRAM module would have many dozens of pins, only a few are shown in FIG. 1C).
However, data from these module outputs will typically be called for at the same time, i.e., on a byte basis. When the microprocessor makes such a call, the length difference inside the connector will cause the data corresponding to the nibble DQ0-DQ3 to arrive at the mother board 12 slightly before nibble DQ4-DQ7, e.g., perhaps on the order of 50 picoseconds or so. That is to say, a 50 ps “skew” is introduced in the byte lane. While this delay is relatively small, it can represent a significant portion of the data valid window on a memory module containing high speed memory chips (e.g., 20% of the data valid window on a DDR3 DRAM module).
To put this problem into further perspective, FIG. 2 shows the timing of the signals comprising the byte lane as they reach the mother board 12. The data is accompanied by a data valid signal, DQS, which is also sent by the module 10 when the byte is called for. Essentially, DQS represents a signal which indicates to the calling entity, e.g., the microprocessor, when the data called for is valid. The DQS signal, as to this particular byte, is also provided on the top contact 20t of the module 10. As is shown, the DQS signal arrives at the motherboard when nibble DQ4-DQ7 also arrives, as they are all provided through the top contacts 20t of the module and the top conductors 22t of the connector 18. However, nibble DQ0-DQ3, outputs to the bottom contacts 20b of the module 10, and thus arrives earlier by virtue of its shorter path through conductors 22b in the connector 18. The result of this skew is that the DQS signal doesn't exactly accurately indicate to the microprocessor when valid data is necessarily present for the entirety of the byte lane.
This problem has been rectified in the prior art by adjusting the lengths of the electrical traces on the mother board. Specifically, the length of the traces between the connector 18 and, for example, the microprocessor on the mother board 12 were lengthened for the “earlier” nibble, DQ0-DQ3 in the present example. In other words, the mother board traces for the earlier nibble would be longer than those for the later nibble, DQ4-DQ7. In so doing, and assuming the increase trace length compensates for the timing differential caused by the connector conductors 22t and 22b, the signals will be provided to the microprocessor at the same time, overcoming this problem.
However, this prior art solution is not optimal. First, it requires the mother board design to account for delays caused by the connector 18 and to specifically engineer the trace lengths. This may be inconvenient. Moreover, an otherwise undesired diversion in the trace length (such as a serpentine) is required, and may not be possible if space does not permit on the mother board.
Second, such lengthening of trace lengths essentially tailors the mother board for a particular connector, rendering the motherboard non-optimal if other types of connectors are to be used. For example, consider the 0-degree connector 18 of FIG. 3. This connectors orients the module 10 perpendicularly to the mother board 12 when mounted, as would be typical in a desktop computer. Moreover, given this configuration, it can be seen that the conductors 22 inside of the connector 18 are of the same length. In other words, the 0-degree connector 18 of FIG. 3 does not cause the same skew problem between nibbles in the byte lane as does the 90-degree connector 18 of FIG. 1B. Therefore, if the trace lengths on the mother board 12 are optimized for a particular type of connector, the use of other connectors would be non-optimal. Hence, adjustment of trace lengths does not make for a universal solution.